INT_AT_BGAP=Val_0x0, CONTINUE_REQ=Val_0x0, STOP_BG_REQ=Val_0x0, RD_WAIT_CTRL=Val_0x0
Block Gap Control Register
| STOP_BG_REQ | Stop at Block Gap Request. This bit is used to stop executing read and write transactions at the next block gap for non-DMA, SDMA, and ADMA transfers. 0 (Val_0x0): Transfer 1 (Val_0x1): Stop |
| CONTINUE_REQ | Continue Request. This bit is used to restart the transaction, which was stopped using the Stop at Block Gap Request (SDMMC_BGAP_CTRL_R[STOP_BG_REQ]). The Host Controller automatically clears this bit when the transaction restarts. If stop at block gap request is set to 0x1, any write to this bit is ignored. 0 (Val_0x0): No affect 1 (Val_0x1): Restart |
| RD_WAIT_CTRL | Read Wait Control. This bit is used to enable the read wait protocol to stop read data using SD_D[2] line if the card supports read wait. Otherwise, the Host Controller has to stop the card clock to hold the read data. 0 (Val_0x0): Disable read wait control 1 (Val_0x1): Enable read wait control |
| INT_AT_BGAP | Interrupt at Block Gap. This bit is valid only in the 4-bit mode of an SDIO card and is used to select a sample point in the interrupt cycle. Setting this bit to 0x1 enables interrupt detection at the block gap for a multiple block transfer. 0 (Val_0x0): Disabled 1 (Val_0x1): Enabled |